Hardware Implementation of HEVC Inverse Transform in 45nm CMOS

Richard Calusdian 
Aaron Stillmaker 

Department of Electrical and Computer Engineering
California State University, Fresno

Abstract

The High Efficiency Video Coding (HEVC) standard relies on the use of the inverse discrete cosine transform (IDCT) to perform video decompression. HEVC has increased the complexity of the decoder and the inverse transform lends itself well to hardware acceleration due to repeated addition and multiplication on unit blocks. A hardware implementation of the inverse quantization and inverse transform, compliant to the HEVC standard, is presented. The design targets the 4x4 inverse quantization and transform performing a synthesis and place & route flow using the Nangate FreePDK45 Open Cell Library. The operational frequency of presented design supports 4K video at up to 30 frames/sec. The core area of the presented design takes up 14 664 μm^and can operate at max. frequency of 367 MHz.

Paper

PATMOS Power Gating Paper
PDF (460 KB),   (c) Copyright 2020, IEEE.

Reference

Richard Calusdian and Aaron Stillmaker and Bevan Baas, "Hardware Implementation of HEVC Inverse Transform in 45nm CMOS," In Proceedings of the IEEE Latin American Symposium on Circuits and Systems (LASCAS) 2020, San José, Costa Rica, February 2020

BibTex

@INPROCEEDINGS{rcalusdian:LASCAS2020,
author = {Richard Calusdian and Aaron Stillmaker},
booktitle = {IEEE Latin American Symposium on Circuits and Systems {LASCAS}},
title = {Hardware Implementation of HEVC Inverse Transform in 45nm CMOS},
year = 2020,
month = feb
}