Impact of Coarse-Grained Power Gate Placement on a Fine-Grained System Design

Shylesh Umapathy 
Aaron Stillmaker 

Department of Electrical and Computer Engineering
California State University, Fresno

Abstract

With the 54th commemoration of Moores law and the intense development of VLSI technology has permitted more and more IP components to be integrated on a single chip. However, factors such as power consumption has been limiting this growth rate. Low power techniques such as clock gating, power gating, dynamic voltage and frequency scaling, body biasing, and many more have emerged as potential solutions. This paper explores power gating technique and presents the design trade-offs between the ring and grid style of power gate placement in a fine-grained system design. The study used 24 physical designs of 12 different sized MAC units ranging from 44 to 320-bit inputs, and extracted various parameters. The results depict that, using a ring style of placement gives an average increase in IR drop of 9.59% when compared to grid style of placement for 128 to 320-bits input MAC unit. The grid style possesses an additional average congestion of 1.66% when compared to ring style of placement for 192 to 320-bits input MAC unit.

Paper

PATMOS Power Gating Paper
PDF (1.0 MB),   (c) Copyright 2019, IEEE.

Reference

Shylesh Umapathy and Aaron Stillmaker, "Impact of Coarse-Grained Power Gate Placement on a Fine-Grained System Design," In Proceedings of the IEEE International Symposium on Power and Timing Modeling, Optimization, and Simulation (PATMOS), Rhodes, Greece, Jul. 2019

BibTex

@INPROCEEDINGS{sumapathy:PATMOS2019,
author = {Shylesh Umapathy and Aaron Stillmaker},
booktitle = {IEEE International Symposium on Power and Timing Modeling, Optimization, and Simulation {PATMOS}},
title = {Impact of Coarse-Grained Power Gate Placement on a Fine-Grained System Design},
year = 2019,
month = jul
}