A Configurable H.265-Compatible Motion Estimation Accelerator Architecture for Realtime 4K Video Encoding in 65 nm CMOS

Michael Braly *
Aaron Stillmaker *
Bevan M. Baas *

*VLSI Computation Laboratory
Department of Electrical and Computer Engineering
University of California, Davis

†Department of Electrical and Computer Engineering
California State University, Fresno

Abstract

The design for a configurable motion estimation accelerator is presented and demonstrated as suitable for realtime digital 4K as well as H.265/HEVC. The design has two 4-KB frame memories necessary to hold the active and reference frames, designed using a standard cell memory technique, with line-based pixel write, and block-based pixel accesses. It computes a 16 pixel sum of absolute differences (SAD)s per cycle, in a 4×4 block, and is pipelined to take advantage of the high throughput block pixel memories. The architecture supports configurable search patterns and threshold-based early termination which allow for run-time tradeoffs to be made between pixel throughput and final quality of result. CMEACC is independently clocked and can operate up to 812 MHz at 1.3 V in 65 nm CMOS, achieving a throughput of 105 MPixel/sec for a single instance while consuming 0.933 pJ×sec/Pixel, and occupying approximately 1.04 mm2 post place-and-route in 65 nm CMOS. While operating at 0.9 V, the presented design consumes 0.393 nJ/Pixel, which scales to 8.06 mW at 22.26 FPS in 720p.

Paper

First Page of the KiloCore MICRO paper
PDF (1.0 MB) [IEEE link],   (c) Copyright 2017, IEEE.

Reference

Michael Braly, Aaron Stillmaker and Bevan Baas, "A Configurable H.265-Compatible Motion Estimation Accelerator Architecture or Realtime 4K Video Encoding in 65nm CMOS," In Proceedings of the IEEE Conference on Dependable and Secure Computing, Taipei, Taiwan, Aug. 2017

BibTex

@INPROCEEDINGS{mbraly:DSC2017,
author = {Michael Braly, Aaron Stillmaker and Bevan M. Baas},
booktitle = {IEEE Conference on Dependable and Secure Computing},
title = {A Configurable H.265-Compatible Motion Estimation Accelerator Architecture for Realtime 4K Video Encoding in 65 nm CMOS},
year = 2017,
month = aug
}