Nan Wang, PHDNan Wang
Associate Professor
Ph.D.

Email: nwang@csufresnio.edu

Office: Engineering East 264

Phone: (559) 278-4415               

Mailing Address: 2320 E. San Ramon Ave., MS/EE 94, Fresno, CA 93740-8030               

LinkedIn Profile: https://www.linkedin.com/in/nan-wang-b4b92712

Faculty Advisor: Asian Christian Student Organization

Spring 2017 Office Hours: Monday, Wednesday: 11am-1pm

More Information about Dr. Wang:

Academic Services:

  • University Graduate Committee, California State University, Fresno
  • LCOE Academic Affair Committee, Lyles College of Engineering, Fresno State
  • Search Committees, Dept. Electrical and Computer Engineering

Current Courses:

  • Microprocessor Systems and Labs
  • Switching Theory and Logic Design
  • Advanced Computer Architecture
  • Advanced VLSI Design Seminar (G)

Editorial and Scholarly Review:

  • Panelist, NSF JUNO2 program solicitation: Japan-US Network Opportunity: R&D for Trustworthy Networking for Smart and Connected Communities.

  • Keynote speaker, IEEE ICCC 2018, IEEE CCWC 2018, IEEE IEMCON 2017, IEEE ICCC 2017, the 1st WV CPS Symposium
  • Program Chair and/or Session Chair, IEEE ICCC 2018, 2017, 2016, IEEE CCWC 2018, IEEE IEMCON 2017, WCSE 2017, the 1st WV CPS Symposium
  • Editorial member, journal of CPS
  • Reviewer, IEEE Tran. CAD ICS, IET Miconano, Plos One, ASTESJ, KSII IIS, and IJERT/IJSTR/IJCET/IJITN journals
  • TPC Member,IEEE WTS 2017, IEEE ISVLSI 2017, IEEE CITS 2017, IEEE ICCT 2017, ACM GLSVLSI 2017, ACM MSE 2017, WCSE 2017, ICITS 2017, ICOSE 2017, IEEE ICCC 2017, 2016

Education:

  • Ph.D., Computer Engineering (2008) - University of Louisiana at Lafayette, Lafayette, Louisiana
  • Master of Science, Computer Engineering (2000) - University of Louisiana at Lafayette, Lafayette, Louisiana
  • Bachelor of Science, Computer Science (1990) - Xiamen University, Xiamen, China

Grants, Honors, and Awards:

  • PI, NSF (National Science Foundation), NeTs Research Grant. “Low Power Bulldog Mote Design”, $424, 612, recommended

Industry Experience:

  • 07/2000 to 05/2002     Hardware Engineer, Hughes Network System, San Diego
  • 07/1990 to 05/1998     Hardware Engineer and Project Manager, BICE, Beijing

Membership & Professional Affiliations:

  • IEEE, member
  • ASEE, member

Publications:

Peer-referred journals

E. Mueller, C. Lane, Y. Mai, P. Valencia and N. Wang, “An Efficient Deterministic Edge Traffic Distribution Network-on-chip Routing Algorithm Design”, in Journal of Communications, Sep. 2018, ISSN: 1796-2021 (Online); 2374-4367 (Print), DOI: 10.12720/jcm.

R. Bindal, M. Shah, and N. Wang, “An Efficient Routing Protocol for Low-Power and Lossy Wireless Sensor Networks”, in Journal of Communications, Sep. 2018, ISSN: 1796-2021 (Online); 2374-4367 (Print), DOI: 10.12720/jcm.

S. Chaturvedi, S. K. Pasumathi, and N. Wang, “Implementation and Performance Analysis of Two Error Detection and Correction Techniques: CRC and Hamming Code”, in International Journal of Interdisciplinary Telecommunications and Networking (IJITN), Vol 10 (1), Jan. 2018, IGI Global, pp. 36-48.

 Y. Mai, Y. Bai and N. Wang, “Performance Comparison and Evaluation of the Routing Protocols for MANETs using NS3”, in Journal of Electrical Engineering, Vol 5, 2017. David Publisher, ISSN 1582-4594. Doi:10.17265/2328-2223/2017.04.001. 2016, pp.187-195.

N. Wang, A. Sanusi, P. Zhao, M. Elgamel and M. Bayoumi, “PMCNOC: A Pipelining Multi-channel Central Caching Network-on-chip Communication Architecture Design,”  in Springer Journal of Signal and Processing, February, 2010

P. Zhao, J. McNeely, P. K. Golconda, S. Venigalla, N. Wang, M. Bayoumi, W. Kuang and L. Downey, “Low power Clocked-pseudo-nmos Flip-Flop for Level Conversion in Dual Supply Systems,” IEEE Transaction on VLSI, 2008.

N. Wang and M. Bayoumi, “System-on-chip communication architecture: dynamic parallel fraction control bus design and test methodologies,” IET Proc. Comp. Digital Tech., Vol. 1, (1), 2007, pp. 1-8 

Peer-reviewed conference paper

S. K. Pasumarthi, G. Fei, and N. Wang, “ EHTC: An Enhanced Huffman Tree Coding Algorithm and its FPGA Implementation”, accepted to the 4th IEEE International Conference on Computer and Communications (IEEE ICCC 2018), Chengdu, China, December, 2018.

S. Umapathy, and N. Wang, “ An Efficient Deterministic NOC Routing Algorithm”, in the 39th Central California Research Symposium, Fresno, California, April, 2018. (Outstanding Engineering Presentation Award).

F. Rodriguez, and N. Wang, “An Efficient MANET Multiple Path Congestion Control AODV Algorithm”, in the 39th Central California Research Symposium, Fresno, California, April, 2018.

S. Umapathy, M. Shah, and N. Wang, “Encircle Routing: An Efficient Deterministic Network on Chip Routing Algorithm”, in Proc. The 8th IEEE Annual Computing and Communication Workshop and Conference (CCWC 2018), Las Vegas, NV, USA, Jan. 2018, pp. 895-899.  

Y. Mai, F. Rodriguez, and N. Wang, “CC-ADOV: An Effective Multiple Paths Congestion Control AODV”, in Proc. The 8th IEEE Annual Computing and Communication Workshop and Conference (CCWC 2018), Las Vegas, NV, USA, January 2018, pp. 1000-1004.

P. Valencia, E. Mueller and N. Wang, “Zigzag: An Efficient Deterministic Network-on-chip Routing Algorithm Design”, in Proc. The 8th IEEE Annual Information Technology, Electronics and Mobile Communication Conference (IEMCON 2017), Vancouver, Canada, October, 2017, pp. 1-5. (Best Session Presentation Award).

E. Mueller and N. Wang, “Network-on-chip Communication Architecture: Routing Algorithm Designs”, in Proc. the 38th Annual Central California Research Symposium, April, 2017.

Y. Bai, Y. Mai, and N. Wang, “Performance Evaluation and Analysis of the Proactive and Reactive Routing Protocols for MANETs”, in Proc. IEEE Wireless Telecommunications Symposium (WTS 2017), Chicago, IL, USA, April 2017, pp.1-5.

O.S.Murkumbi, T.Tankasali and N. Wang, “Efficient Reversible Arithmetic Logic Units Designs and Evaluation”, in Proc. the 2nd International Conference on Electronics Engineering and Informatics (ICEEI 2017), Beijing, China, June 25-27, 2017.

N. Wang, R. Kumar and R. Basavaraj, “Implementation and Performance Evaluation of Pipelining Mechanism in 32-bit MIPS Architecture”, in Proc. The 2nd International Conference on Electronics Engineering and Informatics (ICEEI 2017), Beijing, China, June 25-27, 2017.

N. Wang, and P. Valencia,  “Traffic Allocation: An Efficient  Network-on-chip Routing Algorithm  Design,” in 2nd IEEE International Conf. in Computers and Communications (ICCC 2016), Chengdu, China, October, 2016, pp.2015-2019. (Best Session Presentation Award).

A. Sanusi, N. Wang and M. Bayoumi, “Guaranteeing QoS with the Pipelined Multi-Channel Central Caching NoC Communication Architecture,” in Proc. IEEE Intl. Conf.  System-on-chip (SOCC 08’), September 2008, Newport Beach, California.

N. Wang, A. Sanusi, P. Zhao, M. Elgamel, and M. Bayoumi, “A Multi-Channel Central Caching Network-on-chip Communication Architecture Design,” in Proc. IEEE Conf. Signal and Processing (SIPs 07’), Shanghai, China, September 2007, pp. 487-492.

N. Wang, A. Sanusi and M. Bayoumi, “CTCNOC: A central caching network-on-chip communication architecture design,” in Proc. Intl. Conf. IP Based SOC Design, December 2006, Grenoble, France, pp. 49-52

N. Wang and M. Bayoumi, “DPCI: An Efficient Scalable System-on-chip Communication Architecture,” in Proc. Intl. Conf. IP Based SOC Design, December 2006, Grenoble, France, pp. 77-80

N. Wang and M. Bayoumi, “Dynamic fraction control bus: New SOC on-chip communication architecture design,” in Proc. IEEE Intl. Conf. System-on-chip (SOCC 05’), September 2005, Washington, DC, pp. 199-202

Research Interests:

  • System-on-chip/network-on-chip communication architecture
  • Embedded system
  • FPGA/ASIC design and implementation
  • Real-time computing and VLSI design
  • Mobile Ad Hoc Network (MANET)
  • Wireless Network-on-chip Communication